The invention relates to a floating gate memory cell for data storage applications, and more particularly, to a floating gate memory device having a variable resistance dielectric as a gate insulator.
Computer data storage, in particular random access memory (RAM) has become an increasingly important component of electronic hardware. There are various distinct types of memory devices, distinguished by their speed and data retention characteristic. Dynamic random access memory (DRAM) is a volatile memory characterized by a destructive read. This means that it is necessary to supply voltage to the memory bits at all times, or the information will disappear. Furthermore, each memory element has associated with it a transistor. Static random access memory (SRAM) stores data in a bistable flip-flop, commonly consisting of cross-coupled inverters. It is called xe2x80x9cstaticxe2x80x9d because it will retain a value as long as power is supplied. It is still volatile, i.e. it will lose its contents when the power is switched off, in contrast to ROM. SRAM is usually faster than DRAM, but each bit requires several transistors (about six), so that a lesser number of bits of SRAM fit in the same area as compared to DRAM.
When the gate electrode of a conventional MOSFET is modified so that semi-permanent charge storage inside the gate is possible, the new structure becomes a nonvolatile memory device (floating gate transistor). Nonvolatile memory devices have been extensively used in integrated circuits, such as the electrically alterable read-only memory (EAOM), the erasable-programmable read-only memory (EPROM), and the nonvolatile random-access memory (NVRAM).
In a floating gate transistor, charges are injected from the silicon across a first insulator and stored in the floating gate or at the insulator-oxide interface. The stored charge gives rise to a threshold voltage shift, and the device is at a higher-threshold voltage state. A long retention time is required for nonvolatile memory operation. The retention time is defined as a time when the stored charge decreases to 50% of its initial value. For a well-designed memory device, the charge retention time can be over 100 years. To erase the stored charge and return the device to a xe2x80x9clow-threshold voltage state,xe2x80x9d a high reverse voltage is applied to the gate and/or the device is exposed to UV light. The conventional erase process is relatively slow.
There is a need for a floating gate memory device with decreased erase time and that does not require the application of UV light.
These and other needs are met by embodiments of the present invention which provide a floating gate memory device comprising a substrate and a first insulating layer on the substrate. A floating gate is provided on the first insulating layer, and a second insulating layer is on the floating gate. A control gate is formed on the second insulating layer. At least one of the first or the second insulating layers has a controllably variable resistivity.
In certain embodiments, at least one of the first and second insulating layers consists of a molecular matrix with ionic complexes distributed through the molecular matrix.
With the present invention, the resistivity (or conductivity) can be changed in response to the application of an electric field. By switching the resistivity from a highly resistive state, where charge is retained by the floating gate, to a lower resistivity state, the charge stored on the floating gate can be drained off to the gate electrode.
Other embodiments of the invention also satisfy the above-stated needs by providing a memory device comprising a first insulating layer, a floating gate on the first insulating layer, a second insulating layer on the floating gate, and a control gate on the second insulating layer. At least one of the first and second insulating layers comprises a material switchable between low and high conductivity states in response to an applied electric field.
The earlier stated needs are also met by further aspects of the present invention which provide a memory device comprising a floating gate, an insulating layer on the floating gate, and a control gate on the insulating layer. The insulating layer comprises a molecular matrix with ionic complexes distributed in the molecular matrix.
The earlier stated needs are also met by a still further aspect of the invention which provides a method of operating a floating gate memory device. This method comprises the steps of maintaining an insulating layer between a floating gate and a control gate in a first conductivity state that is sufficient to retain a floating gate charge for at least a predetermined period of time. An electric field is applied to the insulating layer to place the insulating layer in a second conductivity state having at least an order of magnitude greater conductivity than the first conductivity state sufficient to discharge the floating gate charge.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.